Among various solid-state non-volatile memories (NVM) technologies which have been developed rapidly in recent years, high-density and high-speed NVM are especially expected for different applications, such as in modern computing systems and data centers, portable devices, and various consumer electronics. For example, Dynamic Random Access Memory (DRAM) has been used as the main memory in computer systems for decades due to its high density, high speed, and low cost. However, as DRAM is volatile, the stored data cannot be sustained when the power is switched off. Furthermore, there is a continuous demand for the capacity of the main memory, while DRAM faces significant challenges beyond the 20 nm technology node due to various limitations associated with device leakages and retention time. Therefore, intensive research has been carried out to investigate alternative memory technologies to replace DRAM. For example, Spin-Torque Transfer magnetic random access memory (STT-MRAM) has emerged as a promising NVM technology, featuring compelling advantages in scalability, speed, endurance, and power consumption. It has been considered as a competing technology to replace DRAM at the main memory level since it enables non-volatile data retention as well as a significant reduction of power consumption.
However, in STT-MRAM for example, the reliability of data is seriously affected by various factors, such as the variation of the magnetic tunneling junction (MTJ) resistances due to the process-induced statistical parametric variations, the write errors due to switching current threshold distributions of the MTJ and the insufficient write current caused by variations of the nMOS transistor, as well as the read errors due to the read disturbance and memory sensing inaccuracy. Currently, in the example of STT-MRAM, considerable efforts have been made on device design, material improvement, and wafer processing. However, very little work has been done from a coding and signal processing perspective to correct the cell errors of STT-MRAM. Furthermore, for STT-MRAM to be used as the DRAM replacement in the main memory, the error correction coding needs to meet up to both the requirements of high-speed and high-density. These two requirements in general contradict or oppose each other during the code design. The state of the art error correction codes (ECCs) used for NVM, such as STT-MRAM, is the simple Hamming codes or BCH codes. Although the Hamming codes and BCH codes have fast encoder and decoder, it may not be sufficient to satisfy the high-density requirement due to its limited error correction capability associated with the hard-decision decoding (HDD). Furthermore, in the example of STT-MRAM, all the state of the art ECCs for STT-MRAM are non-adaptive with fixed encoders and decoders. The state of the art ECCs are thus generally designed for the worst-case scenarios, which lead to a waste of memory storage density and higher power consumption.
A need therefore exists to provide an error correction method and module for a NVM that seeks to overcome, or at least ameliorate, one or more of the deficiencies of the conventional ECCs mentioned above. It is against this background that the present invention has been developed.